Table of Contents
Chapter 1: The Characteristics of Digital Electronic Design
1.1: Design
1.2: Hierarchy
1.3: Views
1.4: Connectivity
1.5: Spatial Dimensionality
1.6: Summary
Chapter 2: Design Environments
2.1: Introduction
2.2: System Level
2.3: Algorithm Level
2.4: Component Level
2.5: Layout Level
2.6: Summary
Chapter 3: Representation
3.1: Introduction
3.2: General Issues of Representation
3.3: Hierarchy Representation
3.4: View Representation
3.5: Connectivity Representation
3.6: Geometry Representation
3.7: Summary
Chapter 4: Synthesis Tools
4.1: Introduction
4.2: Cell Contents Generation and Manipulation
4.3: Generators of Layout Outside the Cells
4.4: Cells and Their Environment
4.5: Silicon Compilers
4.6: Postlayout Generators
4.7: Summary
Chapter 5: Static Analysis Tools
5.1: Introduction
5.2: Node Extraction
5.3: Geometrical Design-Rule Checkers
5.4: Electrical-Rule Checkers
5.5: Verification
5.6: Summary
Chapter 6: Dynamic Analysis Tools
6.1: Introduction
6.2: Circuit-Level Simulators
6.3: Logic-Level Simulators
6.4: Functional- and Behavioral-Level
6.5: Simulation Issues
6.6: Event-Driven Simulation
6.7: Hardware and Simulation
6.8: Summary
Chapter 7: The Output of Design Aids
7.1: Introduction
7.2: Circuit Boards
7.3: Integrated Circuits
7.4: Implementation Issues
7.5: Summary
Chapter 8: Programmability
8.1: Introduction
8.2: Imperative Programming
8.3: Declarative Programming
8.4: Hierarchy
8.5: Summary
Chapter 9: Graphics
9.1: Introduction
9.2: Display Graphics
9.3: Hardcopy Graphics
9.4: Input Devices
9.5: Summary
Chapter 10: Human Engineering
10.1: Introduction
10.2: Task and User Modeling
10.3: Information Display
10.4: Command Language
10.5: Feedback
10.6: Summary
Chapter 11: Electric
11.1: Introduction
11.2: Representation
11.3: Programmability
11.4: Environments
11.5: Tools
11.6: Designing a Chip
11.7: Summary
Appendices
A: Gerber Format
B: Caltech Intermediate Format
C: GDS II Format
D: Electronic Design Interchange Format
E: EBES Format
F: References for the Entire Book
G: Index